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parasitic extraction
In electronic design automation, parasitic extraction is calculation of the parasitic effects in both the designed devices and the required wiring interconnects of an electronic circuit: parasitic capacitances, parasitic resistances and parasitic inductances, commonly called parasitic devices, parasitic components, or simply parasitics.
The major purpose of parasitic extraction is to create an accurate analog model of the circuit, so that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculation such as: timing analysis; circuit simulation; and signal integrity analysis. Analog circuits are often run in detailed test benches to indicate if the extra extracted parasitics will still allow the designed circuit to function.
== Background ==
In early integrated circuits the impact of the wiring was negligible, and wires were not considered as electrical elements of the circuit. However below the 0.5-micrometre technology node resistance and capacitance of the interconnects started making a significant impact on circuit performance.〔"Automatic Layout Modification", by Michael Reinhardt, (p. 120 )〕 With shrinking process technologies inductance effects of interconnects became important as well.
Major effects of interconnect parasitics include: signal delay, signal noise, IR drop (resistive component of voltage).
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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